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SCE 0110 -Elementos de Lógica Digital I
Flip-Flops, Registradores e Contadores (continuacao)
Prof. Dr. Vanderlei Bonato
Figure 7.24. A four-bit counter with D flip-flops.
Clock
Enable D Q
Q
D Q
Q
D Q
Q
D Q
Q
Q 0
Q 1
Q 2
Q 3
Outputcarry
Figure 7.25. A counter with parallel-load capability.
Enable D Q
Q
Q 0
D Q
Q
Q 1
D Q
Q
Q 2
D Q
Q
Q 3
D 0
D 1
D 2
D 3
LoadClock
Outputcarry
0 1
0 1
0 1
0 1
Figure 7.26. A modulo-6 counter with synchronous reset.
EnableQ 0 Q 1 Q 2
D 0 D 1 D 2 LoadClock
1 0 0 0
Clock
0 1 2 3 4 5 0 1
Clock
Count
Q 0
Q 1
Q 2
(a) Circuit
(b) Timing diagram
Figure 7.27. A modulo-6 counter with asynchronous reset.
T Q
Q Clock
T Q
Q
T Q
Q
1 Q 0 Q 1 Q 2
(a) Circuit
Clock
Q 0
Q 1
Q 2
Count
(b) Timing diagram
0 1 2 3 4 5 0 1 2
Figure 7.28. A two-digit BCD counter.
EnableQ0Q1Q2
D0D1D2
LoadClock
1000
Clock
Q30 D3
EnableQ0Q1Q2
D0D1D2
LoadClock
000
Q30 D3
BCD0
BCD1
Clear
Figure 7.29. Ring counter.
D Q
Q
Clock
D Q
Q
D Q
Q
Start
Q 0 Q 1 Q n 1 ”
Clock
Q 0
Start
Two-bit up-counter
w 0 En
y 0
w 1
y 1 y 2 y 3
1
Q 1 Q 2 Q 3
2-to-4 decoder
Q 1 Q 0
(a) An n -bit ring counter
Clock
Clear
(b) A four-bit ring counter
Mostre o comportamento do contador ring através
de um diagrama de tempo
Figure 7.30. Johnson counter.
D Q
Q
Clock
D Q
Q
D Q
Q
Q 0 Q 1 Q n 1 –
Reset
Mostre o comportamento do contador Johnson através de um diagrama de tempo
Exercícios
• Mostre como obter um FF-D e um FF-T a partir de um FF-JK
• Estudar as questões relacionadas as respostas dos slides seguintes
Figure 7.80. Circuit for Example 7.13.
Figure 7.81. Circuit for Example 7.14.
Figure 7.82. Summary of the behavior of the circuit in Figure 7.81.
Figure 7.84. Circuit for Example 7.16.
Figure P7.1. Timing diagram for problem 7.1.
D
Clock
Figure P7.2. Circuit for problem 7.9.
A
B
C
D
E
Figure P7.3. The circuit for problem 7.18.
T Q
Q
1 T Q
Q
T Q
Q
Q0 Q1 Q2
Clock
Figure P7.4. Circuit for problem 7.19.
Clock
S Q
Q
Clk
R
S Q
Q
Clk
R
Q
Q
J
K
Figure P7.5. A ring oscillator.
f
Figure P7.6. Timing of signals for problem 7.31.
Reset
Interval
100 ns
Figure P7.7. Circuit and timing diagram for problem 7.32.
Q
Clock
D
Q
A
1 0
1 0
1 0
1 0
A
D
Clock
Q
Figure P7.8. Timing diagram for problem 7.33.
1 0
1 0
1 0
1 0
g
f
Start
Clock
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