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Order Reduction of Wideband Digital Predistorters Using Principal Component Analysis Pere L. Gilabert 1 , Gabriel Montoro 1 , David López 2 , Nikolaos Bartzoudis 2 , Eduard Bertran 1 , Miquel Payaró 2 and Alain Hourtane 3 1 Dept. of Signal Theory and Communications, Universitat Politècnica de Catalunya (UPC), c/ Esteve Terradas 7, 08860 Castelldefels, Barcelona, Spain. 2 Centre Tecnològic de Telecomunicacions de Catalunya (CTTC), Parc Mediterrani de la Tecnologia, Av. Carl Friedrich Gauss 7, 08860 Castelldefels, Barcelona, Spain. 3 Aviat Networks, 5200 Great America Parkway, Santa Clara, CA 95054, USA. Abstract — This paper presents how to apply order reduction in wide-band digital predistortion (DPD) linearizers using the principal component analysis (PCA) technique. This method is tested in a wireless backhauling transmitter where four 28 MHz adjacent subcarrier transmission of M-QAM signals are considered. The DPD has to counteract not only the PA nonlinear behavior, but also its dynamics. This may results critical when considering wideband signals since the number of coefficients required to model memory effects can grow dramatically. By applying the PCA technique, the number of essential parameters can be significantly reduced. In addition, a strategy to minimize the computational cost of finding the optimal coefficients is also presented. A test-bed for evaluating the DPD linearization performance of the RF subsystem when PCA is applied was deployed and experimental results are presented in this paper. Index Terms —Digital predistortion, memory effects, order reduction, principal component analysis. I. INTRODUCTION Backhaul infrastructure for mobile networks plays a role of paramount importance in the proper delivery of services requested by end users. Consequently, in the mid-term horizon, it is expected that network operators will invest a significant amount of the budget devoted to network upgrades in backhaul improvement. Wireless backhauling, whose required infrastructure is significantly small, emerges as the perfect cost-effective solution, especially in countries where the deployment of cabled backhauling faces many economic and geographic difficulties. A significant amount of the deployment costs of wireless backhaul solutions is due to shipping and transportation fees. Not surprisingly, the biggest part of these fees is due to the antenna size. Thus, in this scenario, reducing the size of the antennas is a key enabler for capital expenditures (CAPEX) reduction. From a technology perspective, in order to reduce the size of the antennas while keeping the same link quality the output power yielded by the power amplifier (PA) must be maximized, which implies that it must be driven as close to saturation as possible. Clearly, this puts forth the well-known trade-off between power efficiency and linearity, where digital predistortion (DPD) plays a key role to boost the PA performance. When considering wide bandwidth signals (hundreds of MHz) the number of coefficients required in the DPD model to compensate for both nonlinear and memory effects can be significantly high. This has a negative impact in the least squares (LS) based DPD model extraction/adaptation because it increases the computational complexity. To avoid over- fitting and uncertainty, the size of the data set should be at least 20 times the number of the estimated parameters [1]. Several efforts have been made solve the ill-conditioning problem as well as to reduce the model extraction errors when using a small number of data samples in the DPD model extraction [2]. Alternatively, reducing the order of the DPD model has beneficial effects in both the computational complexity and in the conditioning of the data matrices. The idea of using dominant eigenvalues/eigenvectors for reducing the model order was presented in [3],[4]. In this paper, the principal component analysis (PCA) technique is applied to obtain a reduced order DPD basis that is used to update the DPD coefficients according to a conventional LS formulation. In addition, further complexity reduction is proposed by forcing to zero the less significant terms of the matrix that are used to create the new basis. Finally, targeting a future hardware implementation such as in [5],[6], some FPGA and microprocessor implementation issues are also discussed. Fig. 1.Block diagram of the direct learning approach. 978-1-4673-2141-9/13/$31.00 ©2013 IEEE

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Page 1: [IEEE 2013 IEEE/MTT-S International Microwave Symposium - MTT 2013 - Seattle, WA, USA (2013.06.2-2013.06.7)] 2013 IEEE MTT-S International Microwave Symposium Digest (MTT) - Order

Order Reduction of Wideband Digital Predistorters Using Principal Component Analysis

Pere L. Gilabert1, Gabriel Montoro1, David López2, Nikolaos Bartzoudis2, Eduard Bertran1, Miquel Payaró2 and Alain Hourtane3

1Dept. of Signal Theory and Communications, Universitat Politècnica de Catalunya (UPC), c/ Esteve Terradas 7, 08860 Castelldefels, Barcelona, Spain.

2Centre Tecnològic de Telecomunicacions de Catalunya (CTTC), Parc Mediterrani de la Tecnologia, Av. Carl Friedrich Gauss 7, 08860 Castelldefels, Barcelona, Spain.

3Aviat Networks, 5200 Great America Parkway, Santa Clara, CA 95054, USA.

Abstract — This paper presents how to apply order reduction in wide-band digital predistortion (DPD) linearizers using the principal component analysis (PCA) technique. This method is tested in a wireless backhauling transmitter where four 28 MHz adjacent subcarrier transmission of M-QAM signals are considered. The DPD has to counteract not only the PA nonlinear behavior, but also its dynamics. This may results critical when considering wideband signals since the number of coefficients required to model memory effects can grow dramatically. By applying the PCA technique, the number of essential parameterscan be significantly reduced. In addition, a strategy to minimizethe computational cost of finding the optimal coefficients is also presented. A test-bed for evaluating the DPD linearization performance of the RF subsystem when PCA is applied was deployed and experimental results are presented in this paper.

Index Terms —Digital predistortion, memory effects, order reduction, principal component analysis.

I. INTRODUCTION

Backhaul infrastructure for mobile networks plays a role of paramount importance in the proper delivery of services requested by end users. Consequently, in the mid-term horizon, it is expected that network operators will invest a significant amount of the budget devoted to network upgrades in backhaul improvement. Wireless backhauling, whose required infrastructure is significantly small, emerges as the perfect cost-effective solution, especially in countries where the deployment of cabled backhauling faces many economic and geographic difficulties.

A significant amount of the deployment costs of wireless backhaul solutions is due to shipping and transportation fees.Not surprisingly, the biggest part of these fees is due to the antenna size. Thus, in this scenario, reducing the size of the antennas is a key enabler for capital expenditures (CAPEX) reduction.

From a technology perspective, in order to reduce the size of the antennas while keeping the same link quality the outputpower yielded by the power amplifier (PA) must be maximized, which implies that it must be driven as close to saturation as possible. Clearly, this puts forth the well-known trade-off between power efficiency and linearity, where digital

predistortion (DPD) plays a key role to boost the PA performance.

When considering wide bandwidth signals (hundreds of MHz) the number of coefficients required in the DPD model to compensate for both nonlinear and memory effects can be significantly high. This has a negative impact in the least squares (LS) based DPD model extraction/adaptation becauseit increases the computational complexity. To avoid over-fitting and uncertainty, the size of the data set should be at least 20 times the number of the estimated parameters [1].

Several efforts have been made solve the ill-conditioning problem as well as to reduce the model extraction errors when using a small number of data samples in the DPD model extraction [2]. Alternatively, reducing the order of the DPD model has beneficial effects in both the computational complexity and in the conditioning of the data matrices. The idea of using dominant eigenvalues/eigenvectors for reducing the model order was presented in [3],[4]. In this paper, the principal component analysis (PCA) technique is applied to obtain a reduced order DPD basis that is used to update the DPD coefficients according to a conventional LS formulation. In addition, further complexity reduction is proposed by forcing to zero the less significant terms of the matrix that are used to create the new basis. Finally, targeting a future hardware implementation such as in [5],[6], some FPGA and microprocessor implementation issues are also discussed.

Fig. 1.Block diagram of the direct learning approach.

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II. ARCHITECTURE OF THE DIGITAL PREDISTORTER

The DPD strategy followed to identify and update the DPD function is based on the direct learning approach or model reference adaptive system (MRAS) [3], as depicted in Fig. 1.To test the advantages of the PCA model order reduction, the well-known memory polynomial (MP) behavioral model wasconsidered. The input-output relationship of the DPD block is

[ ] [ ] [ ]x n u n d n� � (1)

where the signal d[n] is the additive distortion introduced by the PA. This additive distortion can be estimated as

[ ] nd n � u w (2)

� �0,0 0, 1 1,0 1, 1,..., ,..., ,...,T

P K K Pw w w w� � � ��w is a Mx1vector of coefficients, where M=P·K, P is the polynomial order and K the number of delays in the MP model. Moreover,

11

11 1

[ ], , [ ] [ ] , , [ ],

, [ ] [ ]

PK

n PK K

u n u n u n u n

u n u n

� �

��

�� �

� �� � � �� �

u� �

�is the

1xM data vector containing the MP basis waveforms and where i� (with � � and 0 0� � ) are the most significant sparse delays of the input signal that contribute to characterize memory effects.

Following the direct learning approach, the coefficients can be estimated iteratively using a weighted LS algorithm.

� � 1�� � H Hw U U U e (3)

1i i �� � � �w w w (4)

with � �0 1, , , TL�U u u u� being the LxM data matrix

(n=1, 2,··· L); with 0 1�� � being the weighting factor and where e is the Lx1 vector of the error defined as

0[ ] [ ] [ ]e n y n G u n� � (5)

where 0G is the linear gain of the PA.

III. PRINCIPAL COMPONENT ANALYSIS (PCA)

A. PCA Description

PCA is a well-known technique suitable for converting a basis of observed and eventually correlated data into a basis of uncorrelated data [7]. This property of eliminating redundancies can be used for order reduction in linear regression problems. By considering the standard LSformulation in (2) and (3), the columns of matrix U can be seen as a basis signal, and PCA provides a way to obtain a new basis doing a linear combination of the vectors forming

the columns of U . The reduced-order LxN matrix U� is defined as

�U UP� (6)

with U being the LxM matrix and P a MxN matrix obtained after finding the eigenvalues and eigenvectors of HU U .

1�� �HU U V V (7)

� is the diagonal eigenvalues matrix and

1 2[ , ,..., ]M�V v v v is the MxM matrix of eigenvectors. As

proved in [7], the eigenvalues of the covariance matrix HUUare obtained by doing the product UV , and a higher covariance eigenvalue implies a higher contribution of the corresponding eigenvector in the variance of the basis waveform. For this reason the matrix 1 2[ , ,..., ]N�P v v v is built selecting the N out of M eigenvectors with higher eigenvalue.

B. PCA Implementation Issues

For the DPD implementation in an FPGA, each one of the Nnew estimators, included in U� , have to be calculated in real-time by means of a linear combination of the original estimation terms in U . In fact, only the first row of U� will be calculated in real-time, because the other terms corresponds to the terms calculated in previous FPGA processing clocks and are stored in memory. Therefore, the real-time computational cost in the FPGA is increased by M·N complex products and (M-1)·N complex additions at each FPGA clock. On the contrary, the number of DPD coefficients is reduced from Mto N, and so the amount of data required for estimating or updating these coefficients when using, for example, QR decomposition, RLS, etc. This approach relaxes the computational load of the subsystem responsible for assisting the real-time FPGA device in the task of updating the DPDparameters, such as for example, a soft-core microprocessor (e.g. Xilinx Microblaze) or any other microprocessor device. Moreover, applying order reduction techniques also improves the conditioning of the basis waveforms used [3]. Addressing the additional FPGA implementation challenges of the wide predistorting bandwidth (typically five times the baseband one) falls out the scope of this paper.

C. Further DPD Complexity Reduction

The additive distortion d[n] in (2) is now defined as

[ ] nd n � u w� � (8)

where w� is the new Nx1 vector of coefficients and nu� is the resulting 1xN vector obtained as the linear combination of

n n�u u P� . Similarly, the LS solution in (3) is now defined

using the data matrix U� instead of U .

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In order to reduce the computational load associated to the generation of the new basis, it is possible to set to zero the less relevant elements of the matrix P . As shown in Fig. 2, by defining a threshold for the minimum mean absolute value of the P elements it is possible to prune the original matrix and thus reduce the computational complexity in (6).

IV. EXPERIMENTAL RESULTS

The experimental test-bed is illustrated in Fig. 3. On the transmit side, a multi-band 4 channel configuration (one channel is off) of 64-QAM modulated signals with 14 dB of PAPR at RF and 112 MHz bandwidth, are generated and later predistorted using Matlab. This signal is digitally upconverted to a specific IF and the resulting waveform is loaded into the Arbitrary Waveform Generator (Tektronix AWG7122C) that outputs the signal that will be fed into the Device Under Test (DUT) with 10 bit resolution at 12 Gsamp/s. A trigger signalis provided to the receive instrumentation to enable measurement repeatability. The DUT is the RF unit of an Aviat Networks product used for microwave backhaul applications. The transmit section upconverts an IF signal into one of the user selectable 13 GHz channels featuring tunable power level at the output of the PA.

A highly linear internal receive branch downconverts the PA output signal to IF where it will be sampled for DPD use. A Digital Phosphor Oscilloscope (Tektronix DPO72004C) is used to acquire the IF output signal (PA output sample) with 8 bit resolution and up to 100 Gsamp/s. This signal is then fed into the Matlab testbench which closes the loop and iterates the waveform transmit and receive operations to improve the system quality parameters (EVM, ACPR, BER) after applying the designed DPD technique.

Fig. 4 shows the NMSE between the input and the linearized output for different reduction factors (RDF) and pruning percentages (PP) of P . The PP is defined as the ratio between the number of zeros and the total number of elements of P . Taking into account up to 80% of PP no significant NMSE degradation is appreciated. Moreover, for a RDF = 8 the NMSE degradation is around 13 dB but still providing anacceptable DPD performance. The quality degradation of the DPD versus RDF is quantified in Table I and shown in Fig. 5.

V. CONCLUSION

In this paper the suitability of using the PCA technique to reduce the order of the DPD model has been proved in a wireless backhauling transmitter considering wideband signals. Experimental results showed that despite the inherenttradeoff between the RDF and the DPD performance, considerable order reduction can be made before detecting an important quality loss in linearity. Finally, thanks to the proposed pruning strategy the computational complexity introduced by the PCA technique was reduced.

Fig. 2. Mean of the absolute value of the coefficients of matrix P.

Fig. 3. Wideband DPD test bench.

Fig. 4. NMSE for different reduction factors (RDF) and different pruning percentages (PP).

TABLE IDPD LINEARIZATION PERFORMANCE

ConfigurationACLR (dB) EVM (%)

# Coeff.Lower Upper worst

case CH-#

No DPD -30.0 -30.2 4.2 CH-1 0DPD -37.1 -36.5 1.3 CH-3 189DPD RDF=4 -35.5 -35.6 1.4 CH-3 47DPD RDF=4 & PP=78% -35.5 -35.5 1.6 CH-3 47DPD RDF=8 -33.6 -34.5 1.6 CH-3 24

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Fig. 5. Spectrum plots of a 112 MHz BW multi-channel 64-QAM.

ACKNOWLEDGEMENT

This work was partially supported by Aviat Networks; by the Spanish Ministry of Economy and Competitiveness (MINECO) under projects TEC2011-29126-C03-02 and TEC2011-29006-C03-01; and by the Catalan Government under grants 2009 SGR 1046 and 2010 VALOR 198.

REFERENCES

[1] Ali Soltani Tehrani. “Behavioral modeling of wireless transmitters for distortion mitigation” PhD Thesis. Chalmers University of Technology, Gothenburg, Sweden, Nov. 2012.

[2] L. Guan and A. Zhu, “Optimized Low-Complexity Implementation of Least Squares Based Model Extraction for Digital Predistortion of RF Power Amplifiers,” IEEE Trans. on Microwave Theory and Tech., vol 60, pp. 594-603, March 2012.

[3] R. N. Braithwaite, “General principles and design overview of digital predistortion,” chapter in Digital Processing for Front End in Wireless Communication and Broadcasting, F. Luo (Ed.), Cambridge Univ. Press, 2011, pp. 143-191.

[4] R. Neil Braithwaite, “Wide Bandwidth Adaptive Digital Predistortion of Power Amplifiers Using Reduced Order Memory Correction,” IEEE MTT-S Int. Microwave Symp. Dig., June 2008.

[5] P. L. Gilabert, A. Cesari, G. Montoro, E. Bertran and J. M. Dilhac “Multi Look-Up Table FPGA Implementation of an Adaptive Digital Predistorter for Linearizing RF Power Amplifiers with Memory Effects," IEEE Trans. on Microw. Theory and Tech., vol. 56, pp. 372 - 384, Feb. 2008.

[6] P. L. Gilabert, G. Montoro and E. Bertran ,“FPGA Implementation of a Real-Time NARMA-based Digital Adaptive Predistorter”, IEEE Trans. on Circuits and Systems II, vol. 57, 402-406, July 2011.

[7] I.T. Jolliffe, “Principal Component Analysis,” Springer-Verlag, 2002.

978-1-4673-2141-9/13/$31.00 ©2013 IEEE