Levan BabukhadiaLevan Babukhadia

http://www-d0.fnal.gov/~blevan

FPGA’s for DFEFFPGA’s for DFEF

SUNY at Stony BrookSUNY at Stony Brook

Internal Document, December 14, 2000 Levan Babukhadia

One DFE Mother Board receivestrigger data for two FPS -wedges

phi wedge 1 phi wedge 2

L1 L2

FindClusters

in U-orient(L1U)

FindClusters

in V-orient(L1V)

Report 8 L1 CountsL1U: HEl, HPh, LEl, LPh;L1V: HEl, HPh, LEl, LPh;

to FPSS viaLVDS

Find/UseClusters

in U-orient

Find/UseClusters

in V-orient

Report clusters (max of 12U and 12V) to

FPSSvia

LVDS

L1U OR L1Vfirmware

fits in XCV400 @ 75%.

L1U AND L1Vfirmware

fits in XCV600 @ 95%.

What we know :

Internal Document, December 14, 2000 Levan Babukhadia

– Most elementary components of the DFEF Level 1 and Level 2 (L1/2) algorithms are: 1,2L1U The L1 cluster finder in a given -wedge (specified as 1 or 2, in

the subscript of ) and in one (U) orientation. So, in principle, 1,2L1U only needs to determine the four distinct types [which are: “High Electron” (HEl), “High Photon” (HPh), “Low Electron” (LEl), and “Low Photon” (LPh)] of the L1 cluster counts in this orientation.

1,2L1V The same as 1,2L1U, except for the other (V) orientation.

1,2L2UV The L2 algorithm for potentially re-finding the clusters (unless the clusters identified by 1,2L1U and 1,2L1V could be used) and for determining priority for their reporting. To determine such priorities intelligently, BOTH U and V cluster information must be available and used at the same time, hence the L2 algorithm has to have U and V combined. In other words, there is not much sense in having 1,2L2U and 1,2L2V separately, except for the simplified, but quite possibly most realistic implementation, of the L2 algorithm, in which the first 12 found clusters, starting from the lowest , are to be reported in each orientation; Thus, in this case, U and V would be decoupled.

• Note that 1,2 is used for the above components of the algorithms as these components are identical for the two 1,2-wedges.

NomenclatureNomenclature

Internal Document, December 14, 2000 Levan Babukhadia

– So, at the most fundamental level, the four components of the DFEF L1/2 algorithm on a single DFE MB can be identified as follows:

(1) 1L1 1L1U 1L1V ;

(2) 1L2 1L2UV ;

(3) 2L1 2L1U 2L1V ;

(4) 2L2 2L2UV ;

(i.e. there seems to be no rationale in considering L1U and L1V separately, given that they each would need at least one 400 FPGA.)

– And two more useful abbreviations:• DWDB - Double Wide Daughter Board.

• SWDB - Single Wide Daughter Board.

NomenclatureNomenclature

Internal Document, December 14, 2000 Levan Babukhadia

– There can only be up to 3 FPGA’s on one DWDB, so two of the four components of the DFEF algorithm must be combined in one FPGA.

– Transferring of the 1,2L1 clusters (i.e. not counts) from one FPGA to another is practically impossible (would take too much time).

– Without loss of generality, there appear to be only 4 independent combinations of interest as follows (also indicated is the corresponding estimated usage of FPGA’s):

(1) 1L1+2L1, 1L2, and 2L2 at least >1000, 600, and 600.

(2) 1L1+2L1 and 1L2+2L2 at least >1000 and >~1000.

(3) 1L1, 2L1, and 1L2+2L2 at least 800, 800, and >~800.

(4) 1L1+1L2 and 2L1+2L2 at least 1000 and 1000.

– All of these combinations are feasible to implement from the point of view of the availability of the I/O buses on the DWDB/MB.

– However, there is obvious advantage for the combination (4), both cost-wise and from the point of view of most natural logical break up of the DFEF algorithm between two -wedges.

“Obvious” Constraints for DWDB usage in DFEF“Obvious” Constraints for DWDB usage in DFEF

Internal Document, December 14, 2000 Levan Babukhadia

MB

XCV10001L1+ 1L2

XCV10002L1+ 2L2 Not used

Double-wide DB with BG560 footprints

Proposed Configuration for DFEF with DWDBProposed Configuration for DFEF with DWDB

Price Tag: $2,050

( $1,025 x 2 + $2,050 )

COMMENTS:(1) This is less expensive than the smallest imaginable configuration (see

the following slides).(2) Allows switching to Virtex-E FPGA’s where for the same price one can get

significantly higher speed grade (-6 instead of -4).(3) If this configuration is chosen, would also advocate having one MB/DWDB

with ALL 3 FPGA slots filled with 1K FPGA’s -- should be useful in commissioning!

Internal Document, December 14, 2000 Levan Babukhadia

MB

XCV6001L1

XCV6002L1

XCV800 1L2+2L2

Double-wide DB with BG560 footprints

Smallest Imaginable Configuration for DFEF with DWDBSmallest Imaginable Configuration for DFEF with DWDB

Price Tag: $2,275

( $650 x 2 + $975 )

COMMENTS:(1) L1 algorithms will be rather tight in the 600’s (~95%).(2) May need more than 800 for the L2 for two -wedges,

especially if the cluster finding has to be repeated (cannot transferclusters from the other two FPGA’s in reasonable time).

Internal Document, December 14, 2000 Levan Babukhadia

MB

XCV600L2CFT

XCV600L2CPS

XCV400 L1 CFT/CPS

Double-wide DB with BG560 footprints

Comparison: Default Configuration for CTOC (DWDB)Comparison: Default Configuration for CTOC (DWDB)

Price Tag: $1,700

( $650 x 2 + $400 )

Internal Document, December 14, 2000 Levan Babukhadia

– Must have two SWDB’s so as to be able to access all 10 input links and each SWDB must process one -wedge.

– There can be up to 5 FPGA’s on a SWDB, but a backend (fifth) chip must be present to access output links.

– On each SWDB, one now has to worry about L1 and L2 for that . Then the only two possibilities are:

(1) L1+L2 at least >1000.

(2) L1 and L2 at least >600, and >~600.– (1) is no different than the proposal with DWDB with two 1000

FPGA’s, except: (a) would use two SWDB’s for no real good reason, (b) 1000 FPGA can not go in the backend (maximum being 800) and if it goes elsewhere, then at least one 300 should be put in the backend, or else jumper cables should put across (if possible).

– (2) is more expensive (two -wedges would need 4x$650 > 2x$1025) than the proposal with DWDB (2 1K FPGA’s) and uses 2 DBs.

– Any further break-up of algorithms (say L1 L1U and L1V) would only increase the cost (as well as create other problems).

“Obvious” Constraints for SWDB usage for DFEF“Obvious” Constraints for SWDB usage for DFEF

Internal Document, December 14, 2000 Levan Babukhadia

MBSingle-wide DB with BG432 footprints

XCV6001L1 Not used

XCV6001L2

Not used Not used

Price Tag: $2,000

( $500 x 4 )

Smallest Imaginable Configuration for DFEF with SWDBSmallest Imaginable Configuration for DFEF with SWDB

Single-wide DB with BG432 footprints

XCV6002L1 Not used

XCV6002L2

Not used Not used

COMMENTS:(1) L1 algorithms will be rather tight in the 600’s (~95%).

(2) May need more than 800 for the L2 reporting.(3) Cost is more than with DWDB and two 1000’s.

(4) For this footprint, there are only small size (300, 400, and 600) FPGA’s available in Virtex-E family.

Internal Document, December 14, 2000 Levan Babukhadia

MBSingle-wide DB with BG432 footprints

XCV600Tracks Pt1

XCV400Tracks Pt2

XCV300Trk/Cluster

matching

XCV400Tracks Pt3

XCV400Tracks Pt4

Default Configuration for DFEADefault Configuration for DFEA

Single-wide DB with BG432 footprints

XCV600Tracks Pt1

XCV400Tracks Pt2

XCV300Trk/Cluster

matching

XCV400Tracks Pt3

XCV400Tracks Pt4

Price Tag: $4,000

( $500 x 2 + $400 x 6 + $300 x 2 )

Internal Document, December 14, 2000 Levan Babukhadia

**** NOTE >> General pricing shown-- final price may vary slightly.

-4 -5 -6 -6 -7 -8 -6 -7 -8XCV300 n/a n/a n/a n/a n/a n/a n/a n/a n/aXCV400 $400 $500 $650 n/a n/a n/a $500* $700 $990XCV600 $650 $800 $1,100 n/a n/a n/a n/a n/a n/aXCV800 $975 $1,175 $1,625 n/a n/a n/a $1,175* $1640 $2300XCV1000 $1,025 $1,450 $2,025 $1,025 $1,450 $2,025 n/a n/a n/aXCV1600 n/a n/a n/a $1380 $1930 $2700 n/a n/a n/aXCV2000 n/a n/a n/a $2150 $3010 $4200 n/a n/a n/a

-4 -5 -6 -6 -7 -8 -6 -7 -8XCV300 $235 $280 $400 $150 $210 $300 n/a n/a n/aXCV400 $315 $379 $530 $230 $320 $450 n/a n/a n/aXCV600 $530 $640 $895 $390 $540 $760 n/a n/a n/aXCV800 $786 $943 $1320 n/a n/a n/a n/a n/a n/aXCV1000 n/a n/a n/a n/a n/a n/a n/a n/a n/aXCV1600 n/a n/a n/a n/a n/a n/a n/a n/a n/aXCV2000 n/a n/a n/a n/a n/a n/a n/a n/a n/a

Xilinx VIRTEX FPGA's

BG432VIRTEX 2.5V VIRTEX-E 1.8V VIRTEX-EM 1.8V

VIRTEX 2.5V VIRTEX-E 1.8V VIRTEX-EM 1.8VBG560

* ) -- VIRTEX-EM series FPGA's actually are XCV405 and XCV812 in BG560 footprint.

n/a -- is not available in this size/speed/package/architecture.

Internal Document, December 14, 2000 Levan Babukhadia

-4 -5 -6 -6 -7 -8 -6 -7 -8XCV300 ? ? ? n/a n/a n/a n/a n/a n/aXCV400 $400 $500 $650 n/a n/a n/a $500* ?* ?*XCV600 $650 $800 $1,100 n/a n/a n/a n/a n/a n/aXCV800 $975 $1,175 $1,625 n/a n/a n/a $1,175* ?* ?*XCV1000 $1,025 $1,450 $2,025 $1,025 $1,450 $2,025 n/a n/a n/aXCV1600 n/a n/a n/a ? ? ? n/a n/a n/aXCV2000 n/a n/a n/a ? ? ? n/a n/a n/a

-4 -5 -6 -6 -7 -8 -6 -7 -8XCV300 $300 ? ? ? ? ? n/a n/a n/aXCV400 $400 ? ? ? ? ? n/a n/a n/aXCV600 $500 ? ? ? ? ? n/a n/a n/aXCV800 ? ? ? n/a n/a n/a n/a n/a n/aXCV1000 n/a n/a n/a n/a n/a n/a n/a n/a n/aXCV1600 n/a n/a n/a n/a n/a n/a n/a n/a n/aXCV2000 n/a n/a n/a n/a n/a n/a n/a n/a n/a

Xilinx VIRTEX FPGA's

BG432VIRTEX 2.5V VIRTEX-E 1.8V VIRTEX-EM 1.8V

VIRTEX 2.5V VIRTEX-E 1.8V VIRTEX-EM 1.8VBG560

* ) -- VIRTEX-EM series FPGA's actually are XCV405 and XCV812 in BG560 footprint.

n/a -- is not available in this size/speed/package/architecture.

Internal Document, December 14, 2000 Levan Babukhadia

MB

Single-wide DB with BG432 footprints

400 400

400

400 400

400 400 400

Double-wide DB with BG560 footprints