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8/3/2019 SOC – 10EC129
http://slidepdf.com/reader/full/soc-10ec129 1/10
11/9/20
M.Tech – LVS 1st semester
Faculty – Elumalai.R
SOC – 10EC129
Beyond CMOS scaling
Moore’s Law
Predicts doubling of circuit density every 1.5 to 2 years. Engineering Productivity Gap
Engineering productivity has not
been keeping up with silicon gate
capacity for several years.
Companies have been using larger
design teams, making engineers
work longer hours, etc., but clearly
the limit is being reached.
Motivation for SOC Design
What is driving the industry to develop the SOC design
methodology?
– Higher productivity levels
– Lower overall cost
– Lower overall power
– Smaller form factor
– Higher integration levels
– Rapid development of derivative designs
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What is SOC?
System-on-Chip
An IC that integrates the major functional elements of a
complete end-product into a single chip.
usually contains – reusable IP that are pre-designed modules.
– embedded processor, memory, ASIC blocks
– real-world interface
– mixed-signal blocks
– programmable hardware
Has more than 1000 K gates,
Use nm technology and is not an ASIC.
SOC Challenges
Chip complexity
– Gate count, heterogeneous device technologies
– Signal integrity, timing
Design methodology Testing
Designing SOC thus becomes a task of system integration.
Other Challenging issues in SOC design:
Interface among IPs from different venders
Verification of function
Physical design challenges
System Complexity ChallengesSystem Complexity Challenges
System Complexity = exponentially increasing transistor counts, with
increased diversity (mixed-signal SOC, …)
Reuse (hierarchical design support, heterogeneous SOC integration, reuse
of verification/test/IP)
Verification and test (specification capture, design for verifiability,
verificat ion reuse, system-level and software verification, AMS self-test,
noise-delay fault tests, test reuse)
Cost-driven design optimization (manufacturing cost modeling and
analysis, quality metrics, die-package co-optimization, …)
Embedded software design (platform-based system design methodologies,
software verification/analysis, co-design w/HW)
Reliable implementation platforms (predictable chip implementation onto
multiple fabrics, higher-level handoff)
Design process management (team size / geog distribution, data mgmt,collaborative design, process improvement)
Design Metrics and Techniques for SOCDesign Metrics and Techniques for SOCDesign Metrics and Techniques for SOCDesign Metrics and Techniques for SOC Area
Cell area Wirelength
Timing Gate Interconnect
Power Dynamic Static Leakage
Signal Integrity Crosstalk (capacitive, inductive) Supply voltage drop (IR drop, LdI/dt)
Reliability Variation (Vdd, thermal, process variation (tox, BEOL)) Electromigration Hot electron effect (SEU)
Cost minimization
Synthesis (technology mapping)
Placement, routing
Performance optimization
Logic transformation, transistor sizing
Buffering, re-routing
Power minimization
Gating (sleep transistors), variant Vdd
Process optimization
Dual-Vth
Signal Integrity
Sizing, net ordering, shielding
P/G design, placement, synthesis
Reliability
Statistical design optimization
Design margin
80% of System in Embedded SW
• Hardware is not sufficient to build an SoC platform
• 70-80% of the system will be implemented in software
– Product differentiation will move to software from
silicon
–Many IC companies hire more software designers
than IC designers• Standard platforms with software differentiation will
be the trend
– Example: in Set-top box market, manufacturers are
converting from 7 different chips to 1 chip with 7
different application SW
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Efforts in Standardization
• Defacto bus standards – AMBA, Core Connect, etc.
• VSIA (The Virtual Socket Interface (VSI) Alliance, formed in 1996
to foster the development and recognition of standards for designing
and integrating reusable blocks of IP) is involved in developing
standards in SoC design to promote widespread use of;
– on-chip bus attributes
– IP design exchange format
– specifications for signal integrity, soft/hard IP modeling,
functional verification, test data formats
– documentation standards
– test access architecture standard
–VCID for tracking IP
– IP protection, IP quality • IEEE testing standard (P1500)
pp. 15
SoC Example
pp. 16
SoC Architecture
pp. 17
TI OMAP5910 Dual-Core Processor Productivity of IP Reusing
2009
Reused 76%
New 24%
100 million
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Why must IP Reuse?
Design productivity crisis:
Divergence of potential design complexityand designer productivity
TTD :TTD :TTD :TTD : The best approach for desi gning moderately sized and complexThe best approach for desi gning moderately sized and complexThe best approach for desi gning moderately sized and complexThe best approach for desi gning moderately sized and complex
ASICs, consisting primarily of new logic (little if any reu se) on DSM (deep subASICs, consisting primarily of new logic (little if any reuse) on DSM (deep subASICs, consisting primarily of new logic (little if any reu se) on DSM (deep subASICs, consisting primarily of new logic (little if any reuse) on DSM (deep sub
micron) processes, without a significant utilization of hierarchical designmicron) processes, without a significant utilization of hierarchical designmicron) processes, without a significant utilization of hierarchical designmicron) processes, without a significant utilization of hierarchical design
BBD is behaviorally modeled at the system level, where
hardware/software trade-offs and functional hardware/software
co-verification using software simulation and/or hardware
emulation is performed. The new design components are then
partitioned and mapped onto specified functional RTL blocks,
which are then designed to budgeted timing, power, and area
constraints.
The design team is becoming more application-specific, and subsystems,
such as embedded processing, digital data compression, and errorcorrection, are required.
Multiple design teams are formed to work on specific parts of the design.
ASIC engineers are having difficulty developing realistic and
comprehensive test benches.
Interface timing errors between subsystems are increasing dramatically.
The design team is looking for VCs outside of their group to help accelerate
product development.
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What is platform?
– A stable core-based architecture for a target application
– Can be rapidly extended and customized
What are the benefits of a platform?
– Major benefits are
• Increased productivity – Derivative designs can be easily created
• Using software or hardware modifications
• Reduces the design time and increasing success rate
– Diverse applications each require a different platform
• Example of application
– Bluetooth platform
– AMBA bus and ARM TDMI CPU based
PBD encompasses the cumulative capabilities of the TDD and
BBD technologies, plus extensive design reuse and design
hierarchy. PBD can decrease the overall TTM for first
products, and expand the opportunities and speed of
delivering derivative products.
System which requires PBD technology are,
A significant number of functional designs are repeated within and across
groups, yet little reuse is occurring between projects, and what does
occur is at RTL.
New convergence markets cannot be engaged with existing expertise and
resources.
Functional design bugs are causing multiple design iterations and/or re-
spins.
The competition is getting to market first and getting derivative products
out faster.
Project post-mortems have shown that architectural trade-offs
(hardware/software, VC selections) have been suboptimal. Changes
in the derivative products are abandoned because of the risk of
introducing errors.
ICs are spending too much time on the test equipment during
production, thus raising overall costs.
Pre-existing VCs must be constantly redesigned.
Assignment on TTD, BBD and PBD
Assignment on personal reuse portfolio, resource reuse portfolio
and virtual component reuse portfolio
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Comparison between SOC, SIP and SOB
SOC
1. A system-on-chip is a highly integrated, single-chip design using
third-party and internal intellectual property. The IP can be either
a behavioral or physical description of standard components, and
the SoC can contain analog, digital or mixed-signal circuits.
2. A key advantage of SoC technology is the ability to reduce theperformance limitations that result from the system board delays
of going on- and off-chip.
3. Increases reliability for the system
4. Lowers overall system costs, because of fewer discrete
components on the board.
5. High productivity.
6. Low power consumption Ex- mobile phone
SoC continued—
7. TTM (time to market) is faster.
8. Low cost because of high production
9. Highest clock rate can be obtained.
Limitations of SOC
1. The most critical hurdle centers on the IP and its integration
into the design.
2. The integration process becomes more difficult if common
interfaces are not provided for use in the IP modules.
3.Once the integration is achieved, a major effort is needed for
verification of the design before final release. Such verification can
account for more than 60 percent of the total design cycle.
4. More-costly and -sophisticated EDA tools to support both
integration and verification
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SoC Continued –
5. These chips become more complicated, there is a need to push
for more-advanced silicon processes, to attain smaller die size and
lower power.
6. The NRE (non recurring expenses) hurdle for SoC development
can be quite significant when you include IP investment, EDA tools
and silicon process NRE and processing.
Benefits of SOC Technology
– Higher productivity levels , – Lower overall cost
– Lower overall power, – Smaller form factor
– Higher integration levels, – Rapid development of derivative
designsmarket-driven forces for change are:
Shrinking product design schedules and life spans
Conforming products to complex interoperability standards, either
de jure (type approval in communications markets) or de facto
(cable companies acceptance of the set-top market)
Lack of time for product iterations due to implementation errors: a
failure to hit market windows equals product death
Converging communications and computing into single products
and chipsets
Definition of SiP
System in Package (SiP) is a combination of multiple
active electronic components of different functionality,
assembled in a single unit that provides multiple
functions associated with a system or sub-system. A SiP
may optionally contain passives, MEMS, optical
components and other packages and devices.
Key areas of application for SiP designs include wireless products
(GPS modules, Bluetooth solutions, 802.11 modems) and portable
products where there is a need for a combination of large memory
(SDRAM, flash, SRAM), and digital-logic or mixed-signal designs
that require very sophisticated analog design.
SiPs are usually segmented into three technology types: modules
(single- or multichip), stacked dice and 3-D packaging.
SIP cont –
Modules are standard packages incorporating one or more
horizontally arranged dice with chip-level interconnects (wire
bond or flip-chip) and optional surface-mounted passive and active
components mounted on a substrate. The substrate provides
interchip connections, controlled-impedance lines, and grounding
structures; it also has a protective casing.
Stacked-dice packaging consists of two or more vertically stacked
dice with chip-level interconnects (wire bonds) to a substrate, all
enclosed in a standard-package format.
3-D packaging is a combination of standard prepackaged devices or
components using laminate, ceramic, flex or lead-frame substrates,
all stacked vertically with package-level interconnects.
SIP continued –
Advantages of SIP
1. SiP provides more integration flexibility
2. Faster time to market because SiP development time is shorter
since the components do not require as much design verification at
the functional level.
3. Lower R&D cost4. Lower NRE cost
5. If a complicated substrate is limited only to the SiP module,
then the entire system board does not require as many layers or
impedance control. That reduces the system pc board costs and
allows changes to be focused on the SiP itself, rather than on the
entire system board.
SiP cont –
Limitation of SIP
1. Higher cost and development time for many new packaging
technologies compared with those for standard off-the-shelf
packages.
2. Many of the EDA tools for electrical/mechanical system designs
for high-speed applications, as seen in SiPs, are not commercially
available and thus require in-house development.
3. The overall performance, cost, size, and functionally of a SiP will
be limited by both on-chip interconnects of the individual
microchips as well as by off-chip interconnects.
4.
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Comparison of SOC and SIP System on Board (SOB)
The system is integrated on a printed circuit board,
single layer or multilayer based on the complexity of the
system. The inter connection between the system is done
using copper or gold plated copper clad tracks.
Advantages;
1. Since the system assembled on board, alteration in the
interconnection design and application can be done easily.
2. The system cost is very less, because the base material is cheap
3. Time to market is fast
4. System development cost depends on the integration cost and
individual product cost and it is normally high.
SOB cont –
Limitations;
1. The system speed is limited because of external interferences,
capacitance between tracks, impedance between the layers, ground
jumping etc.
2. The reliability of the system is poor because of many component
3. System cost is more.
4.
SOC and Productivity
Two key design technologies are emerging to address the
productivity side of SOC.
1. Technologies, integration platform and
2. Interface-based design, represent an amalgam of design
principles, tools, architectures, methodologies, and management.
Design Reuse Options
• Option 1: chip-level reuse
– Fewer chips designed, HW programmable
– Undifferentiated silicon
• Option 2: processor-level reuse or software reuse
– Chip = processors + memory
– Big SW, little hardware model – Undifferentiated silicon
• Option 3: widespread reuse
– High-value, domain specific reusable blocks
– Differentiated silicon
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Examples of IP Blocks in Use today
• RISC: ARM, MIPS, PowerPC, SPARC
• CISC: 680x0 x86
• Interfaces: USB, PCI, UART, Rambus
• Encryptions: DES, AES• Multimedia” JPEG coder, MPEG decoder
• Networking: ATM switch, Ethernet
• Microcontroller: HC11, etc.
• DSP: Oak, TI, etc.
SoC is forcing companies to develop high-quality IP
blocks to stay in business
Reuse Methodology Manual (RMM)
Promoted by Synopsys and Mentor Graphics
Purpose of the RMM
Allow developers to consistently produce high-quality, reusable macros
Provide integrators with insights into how to select qualified IP
Integrate IP into System-on-Chip (SOC) designs
Broadly accepted by SoC Industry
Soft IP: Configurable and Portable IP
Soft macro deliverables
Documentation
RTL code, both Verilog and VHDL
Synthesis scripts that work for a variety of technology libraries
Models and test benches for verifying the macro in the chip environment
Installation scripts
Creation of the Deliverables
-Clocking, registers andavoiding accidental latches
-Partitioning-VHDL Specific Guidelines
-Verification of compliance
Simple, regular structures areeasier to get functionally correct,
to verify, and to synthesize
-Physical design issues-Timing and synthesis issues-Functional design issues-Verification strategies
-Manufacturing test
-Based on a bottom-upsynthesis strategy-A robust set of timing
budgets
Productization -Simulation
-Silicon prototyping
Key IdeaDesignGuidelines
Coding Guidelines
SynthesisGuidelines
VerificationMethodology
Why Low Power?Why Low Power?Why Low Power?Why Low Power?
Limited Battery Capacity (Mobile Devices)
For Minimal Heat Dissipation (Heat Sink, Cooler, System
Size/Weight/Cost)
For Chip/System Reliability
Save Energy; it’s limited after all!
Power-Critical Applications ;
Heat Dissipation Requirement
Power/Ground Metal Line Width
Power/Ground Bounce due to IR drop
Energy-Critical Applications ;
Battery Lifetime
Heat Dissipation Requirement
Applications for Low Power TechnologyApplications for Low Power TechnologyApplications for Low Power TechnologyApplications for Low Power Technology
Medical ; Implantable hearing-aid, cardiac pacemaker
Mobile Devices ; cellular phone
Military Devices ;
Hard-to-access points ; Space
Too-many-to-access points ; Sensors/Actuators in Ubiquitous World
Methods of reducing the power in SOC
Structural Techniques
Voltage Islands
Multi-threshold devices
Multi-oxide devices
Minimize capacitance
by custom design
Power efficient circuits
Parallelism in
micro-architecture
Dynamic Techniques
Clock gating
Data gating
Power gating
Variable frequency
Variable voltage supply
Variable device threshold
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