Levan BabukhadiaLevan Babukhadia

D Collaboration Meeting, February 7 - 9, 2001, FermilabD Collaboration Meeting, February 7 - 9, 2001, Fermilab

http://www-d0.fnal.gov/~blevan/upgrade.html

Status of L1 FirmwareStatus of L1 Firmware

SUNY at Stony BrookSUNY at Stony Brook

DØ Collaboration Meeting, February 7 - 9, 2001, Fermilab Levan Babukhadia

Levan BabukhadiaMrinmoy Bhattacharjee

Jerry BlazeyBrian ConnollySatish DaseiPaul GrannisSteve Lynn

Manuel MartinJamieson Olsen

Ricardo RodrigezQichun Xu

… for the DFE firmware group… for the DFE firmware group

DØ Collaboration Meeting, February 7 - 9, 2001, Fermilab Levan Babukhadia

Steps to Firmware CertificationSteps to Firmware Certification

– Design algorithms for board / functionality– Write VHDL code, pipelined design– Behavioral Simulations: SoftBench, TestVectors– Synthesis/constraints (GCkl buffers, clock to out,…)– Implementation/constraints (board layout, clocks,

skews on nets, etc.), resources, speed– Timing Simulations: same SoftBench, TestVectors

( ! )– TestStand - download in a target hardware/FPGA

and run with the same TestVectors ( ! )– Board/Functionality certified– SoftBench for multi-board/FPGA chain, propagate

TVs– Chain TestStand with the same TVs– Firmware certified

DØ Collaboration Meeting, February 7 - 9, 2001, Fermilab Levan Babukhadia

DØ Collaboration Meeting, February 7 - 9, 2001, Fermilab Levan Babukhadia

Skew / De-SkewSkew / De-Skew

Data are skewed across LVDSs (out of AFEs) worse than expected. 8ns across 4(5) LVDSs out of AFE8(12), degrading by about

1ns through each tier of DFE boards. (Expected was <1/4 cycle of RF clock).

As a result, can not remove skew across different DFE boards. This means that we need to re-synchronize in every DFE board!

So, had to significantly modify existing de-skewing algorithm from synchronizing clocks (1/4 RF cycle) to synchronizing records (1 RF cycle).

Synchronization of records is different for L1 and L2. Therefore two flavors of the algorithm are needed.

The L1 flavor now works in functional as well as in timing simulations for 10 links (which is the maximum number per any DFE board)!

Work is in progress on the L2 flavor. Expected in 1 week.

DØ Collaboration Meeting, February 7 - 9, 2001, Fermilab Levan Babukhadia

CFT/CPS AxialCFT/CPS Axial

– DFEA (80) : Jamieson• 4 FPGAs (each for tracks in each Pt bin) — done (also to L1MU)• Backend (5-th) FPGA CPS cluster finding and track matching

– Firmware nearly done (H/L, phi-bias), but Ok for Feb. 26.– Developing SoftBench (a la FPS -> Levan)

– CTOC (8) : Brian/Ricardo [ Juan ]• Both L1/L2 firmware completed and tested in TestStand for 8

links• Minor issues and additions will be addressed by Brian/Ricardo• Need changes because of TT modifications ( Levan/Manuel )

– CTQD (4) : Steve (new)• L2CFT completed functionally with some minor issue [ Pavel ]• Needs implementation, L2CPS, and all of this tested in the

hardware• Can not expect this sooner than a couple of months

– CTTT (1) : Levan/Manuel [ Jerry ]• Expect few TTs in a couple of weeks. • No issues of implementation difficulties foreseen.

DØ Collaboration Meeting, February 7 - 9, 2001, Fermilab Levan Babukhadia

CPS StereoCPS Stereo

– DFES (10) : Qichun• Not part of L1 trigger.• VHDL tested at the functional level only.• Develop SoftBench and TestVectors, synthesis,

implementation, TestStand in 1-2 months.

– CPSS (4) : Qichun• Not started yet.

DØ Collaboration Meeting, February 7 - 9, 2001, Fermilab Levan Babukhadia

FPSFPS

– DFEF (32) : Levan• L1 done (passed TestStand). • L2 simplified algorithm in place, need proper functional model

of Xilinx RAMs to test behavioral simulations. • As needed, develop L2 priority reporting to better take care

of truncation

– FPSS (4) : Mrinmoy• L1 done (passed TestStand).• Develop and implements L2 algorithm

– FPTT (1) : Satish• L1 done (passed TestStand).• Working on a generic L1 -> L3 sender. Expect working module

by Feb. 19. It will then be integrated in virtually all DFE boards.

DØ Collaboration Meeting, February 7 - 9, 2001, Fermilab Levan Babukhadia

0% 20% 40% 60% 80% 100% 120%

L1->L1 DFEA ( Jamieson[Kin] )

L1->L2 DFEA ( Jamieson[Kin] )

L1->L1 CTOC ( Ricardo[Juan] )

L1->L2/3 CTOC ( Ricardo[Juan] )

L1->L2 CTQD ( Steve[Pavel] )

L1->L1/3 CTTT (Levan/Manuel )

L1->L2/3 DFES ( Quichan)

L1->L2 CPSS ( ?! )

L1->L1 DFEF ( Levan )

L1->L2 DFEF ( Levan )

L1->L1 FPSS ( Mrinmoy )

L1->L2/3 FPSS (Mrinmoy )

L1->L1 FPTT ( Satish )

L1->L3 FPTT ( Satish )

Design/Algorithm Firmware/Functionality Implementation Test Stand

http://www-d0.fnal.gov/~blevan/upgrade.html

DØ Collaboration Meeting, February 7 - 9, 2001, Fermilab Levan Babukhadia

http://www-d0.fnal.gov/~blevan/upgrade.html

Subsystem ( People Assigned ) Design/AlgorithmFirmware/Functionality I mplementation Test Stand

L1- >L1 DFEA ( J amieson [Kin] ) 90% 90% 80% 80%

L1- >L2 DFEA ( J amieson [Kin] ) 90% 90% 80% 80%

L1- >L1 CTOC ( Ricardo [J uan] ) 95% 90% 90% 90%

L1- >L2/3 CTOC ( Ricardo [J uan] ) 90% 90% 90% 90%

L1- >L2 CTQD ( Steve [Pavel] ) 60% 60% 5% 5%

L1- >L1/3 CTTT ( Levan/Manuel ) 80% 30% 20% 5%

L1- >L2/3 DFES ( Quichan ) 90% 75% 30% 5%

L1- >L2 CPSS ( ?! ) 5% 5% 5% 5%

L1- >L1 DFEF ( Levan ) 100% 100% 100% 100%

L1- >L2 DFEF ( Levan ) 75% 30% 5% 5%

L1- >L1 FPSS ( Mrinmoy ) 100% 100% 100% 100%

L1- >L2/3 FPSS ( Mrinmoy ) 50% 20% 5% 5%

L1- >L1 FPTT ( Satish ) 100% 100% 100% 100%

L1- >L3 FPTT ( Satish ) 80% 80% 60% 5%

DØ Collaboration Meeting, February 7 - 9, 2001, Fermilab Levan Babukhadia

Chain TestChain Test

– L1 CFT/CPSAx:• DFEA & CTOC tested in TestStand by 2/12 ( Jamieson,

Brian ).• CTTT track and hit triggers by 2/19 ( Levan/Manuel ).• System SoftBench by 2/19 ( Levan ).• System (1DFEA + 2CTOC + CTTT) TestStand by 2/26 (all).

– L1 FPS:• Chain SoftBench successful last week! Implemented DFEF +

FPSS + FPTT. Crucial to obtain “chain” TestVectors, to check board-to-board communications, …

• System (1DFEF + 2FPSS + FPTT) TestStand next.

DØ Collaboration Meeting, February 7 - 9, 2001, Fermilab Levan Babukhadia

SummarySummary

– Firmware in good shape, hardware lagging

– L1 CFT/CPSAx track and hit trigger by April 2• DFEA, CTOC in board TestStand by 2/19.• CTTT functional by 2/19.• Integrate Synchronization by 2/26.• Integrate L3 Sender by 2/26.• Chain certified by 3/5.

– L1 FPS trigger by April 2• Chain certified by 3/5 (could slip as L1 CFT/CPSAx has

higher priority).