Last month’s openingepisode explained (amongother things) the basic oper-ating principles of JFETs.JFETs are low-power devices

with a very high input resistanceand invariably operate in the deple-tion mode, i.e., they pass maximumcurrent when the gate bias is zero,and the current is reduced (‘deplet-ed’) by reverse-biasing the gate terminal.

Most JFETs are n-channel(rather than p-channel) devices.Two of the oldest and best knownn-channel JFETs are the 2N3819and the MPF102, which are usuallyhoused in TO92 plastic packageswith the connections shown inFigure 1; Figure 2 lists the basiccharacteristics of these two devices.

This month’s article looks atbasic usage information and appli-cations of JFETs. All practical cir-cuits shown here are specificallydesigned around the 2N3819, butwill operate equally well whenusing the MPF102.

JFET BIASING

The JFET can be used as a lin-ear amplifier by reverse-biasing itsgate relative to its source terminal,thus driving it into the linear region.Three basic JFET biasing techniquesare in common use. The simplest ofthese is the ‘self-biasing’ systemshown in Figure 3, in which thegate is grounded via Rg, and anycurrent flowing in Rs drives thesource positive relative to the gate,thus generating reverse bias.

Suppose that an ID of 1mA iswanted, and that a VGS bias of -2V2is needed to set this condition; thecorrect bias can obviously beobtained by giving Rs a value of2k2; if ID tends to fall for some rea-son, VGS naturally falls as well, andthus makes ID increase and counterthe original change; the bias is thusself-regulating via negative feed-back.

In practice, the VGS value need-ed to set a given ID varies widelybetween individual JFETS, and theonly sure way of getting a precise IDvalue in this system is to make Rs avariable resistor; the system is, how-ever, accurate enough for many

applications, and is the most widelyused of the three biasing methods.

A more accurate way of biasingthe JFET is via the ‘offset’ system ofFigure 4(a), in which divider R1-R2applies a fixed positive bias to thegate via Rg, and the source voltageequals this voltage minusVGS. If the gate voltage islarge relative to VGS, ID isset mainly by Rs and is notgreatly influenced by VGS

variations. This system thusenables ID values to be setwith good accuracy andwithout need for individualcomponent selection.Similar results can beobtained by grounding thegate and taking the bot-tom of Rs to a large negative volt-age, as in Figure 4(b).

The third type of biasing systemis shown in Figure 5, in which con-stant-current generator Q2 sets theID, irrespective of the JFET character-istics. This system gives excellentbiasing stability, but at the expenseof increased circuit complexity and cost.

In the three biasing systemsdescribed, Rg can have any value upto 10M, the top limit being imposedby the volt drop across Rg causedby gate leakage currents, which mayupset the gate bias.

SOURCE FOLLOWER CIRCUITS

When used as linear amplifiers,JFETs are usually used in either thesource follower (common drain) orcommon-source modes. The sourcefollower gives a very high inputimpedance and near-unity voltagegain (hence the alternative title of‘voltage follower’).

Figure 6 shows a simple self-biasing (via RV1) source follower;RV1 is used to set a quiescent R2volt-drop of 5V6. The circuit’s actualinput-to-output voltage gain is 0.95.A degree of bootstrapping isapplied to R3 and increases its effec-tive impedance; the circuit’s actualinput impedance is 10M shunted by10pF, i.e., it is 10M at very low fre-quencies, falling to 1M0 at about16kHz and 100k at 160kHz, etc.

Figure 7 shows a source follow-

er with offset gate biasing. Overallvoltage gain is about 0.95. C2 is abootstrapping capacitor and raisesthe input impedance to 44M, shunt-ed by 10pF.

Figure 8 shows a hybrid (JFETplus bipolar) source follower. Offsetbiasing is applied via R1-R2, andconstant-current generator Q2 actsas a very high-impedance sourceload, giving the circuit an overallvoltage gain of 0.99. C2 bootstrapsR3’s effective impedance up to

PRINCIPLES AND CIRCUITSPart 2

by Ray Marston Ray Marston looks atpractical JFET circuits inthis second episode ofthis four-part series.

FET

Field-Effect Transistors

Figure 1.Outline and

connections ofthe 2N3819 andMPF102 JFETs.

Parameter 2N3918 MPF102

VDS max (= max. drain-to-source voltage) 25V 25VVDG max (= max. drain-to-gate voltage) 25V 25VVGS max (= max. gate-to-source voltage) -25V -25VIDSS (= drain-to-source current with VGS = 0V) 2-20mA 2-20mAIGSS max (= gate leakage current at 25° C) 2nA 2nAPT max (= max. power dissipation, in free air) 200mW 310mW

Figure 2. Basic characteristics of the 2N3819 and MPF102 n-channel JFETs.

Figure 3. Basic JFET ‘self-biasing’ system.

1 JUNE 2000/Nuts & Volts Magazine ©T & L Publications, Inc. All rights reserved.

Figure 4. Basic JFET

‘offset-biasing’system.

Figure 5. Basic JFET ‘constant-current’ biasing

system.Figure 6. Self-biasing

source-follower. Zin = 10M.

1000M, which is shunted by theJFET’s gate impedance; the inputimpedance of the complete circuitis 500M, shunted by 10pF.

Note then if the high effectivevalue of input impedance of thiscircuit is to be maintained, theoutput must either be taken toexternal loads via an additionalemitter follower stage (as showndotted in the diagram) or must betaken only to fairly high imped-ance loads.

COMMON SOURCE AMPLIFIERS

Figure 9 shows a simple self-biasing common source amplifier;RV1 is used to set a quiescent5V6 across R3. The RV1-R2 bias-ing network is AC-decoupled viaC2, and the circuit gives a voltagegain of 21dB (= x12), and has a±3dB frequency response thatspans 15Hz to 250kHz and aninput impedance of 2M2 shuntedby 50pF. (This high shunt value isdue to Miller feedback, whichmultiplies the JFET’s effectivegate-to-drain capacitance by thecircuit’s x12 Av value.)

Figure 10 shows a simple self-biasing headphone amplifier thatcan be used with headphoneimpedances of 1k0 or greater. Ithas a built-in volume control(RV1), has an input impedance of2M2, and can use any supply inthe 9V to 18V range.

Figure 11 shows a self-biasingadd-on pre-amplifier that gives avoltage gain in excess of 20dB,has a bandwidth that extendsbeyond 100kHz, and has an inputimpedance of 2M2. It can beused with any amplifier that canprovide a 9V to 18V powersource.

JFET common source ampli-fiers can — when very high biasingaccuracy is needed — be designedusing either the ‘offset’ or ‘con-stant-current’ biasing technique.Figures 12 and 13 show circuits ofthese types. Note that the ‘offset’circuit of Figure 12 can be usedwith supplies in the range 16V to20V only, while the hybrid circuitof Figure 13 can be used with anysupply in the 12V to 20V range.Both circuits give a voltage gain of21dB, a ±3dB bandwidth of 15Hzto 250kHz, and an input imped-

ance of 2M2.

DC VOLTMETERS

Figure 14 shows a JFET used tomake a very simple and basic three-range DC voltmeter with a maxi-mum FSD sensitivity of 0.5V and aninput impedance of 11M1. Here,R6-RV2 and R7 form a potentialdivider across the 12V supply and —if the R7-RV2 junction is used as thecircuit’s zero-voltage point — setsthe top of R6 at +8V and the bot-tom of R7 at -4V. Q1 is used as asource follower, with its gategrounded via the R1 to R4 networkand is offset biased by taking itssource to -4V via R5; it consumesabout 1mA of drain current.

In Figure 14, R6-RV2 and Q1-R5act as a Wheatstone bridge net-work, and RV2 is adjusted so thatthe bridge is balanced and zero cur-rent flows in the meter in theabsence of an input voltage at Q1gate. Any voltage applied to Q1gate then drives the bridge out ofbalance by a proportional amount,which can be read directly on themeter.

R1 to R3 form a range multipli-er network that — when RV1 is cor-rectly adjusted — gives FSD ranges

of 0.5V, 5V, and 50V. R4 protectsQ1’s gate against damage if exces-sive input voltage is applied to thecircuit.

To use the Figure 14 circuit,first trim RV2 to give zero meterreading in the absence of an inputvoltage, and then connect an accu-rate 0.5V DC to the input and trimRV1 to give a precise full-scalemeter reading. Repeat these adjust-ments until consistent zero and full-scale readings are obtained; theunit is then ready for use.

In practice, this very simple cir-cuit tends to drift with variations insupply voltage and temperature,and fairly frequent trimming of thezero control is needed. Drift can begreatly reduced by using a zener-stabilized 12V supply.

Figure 15 shows an improvedlow-drift version of the JFET volt-meter. Q1 and Q2 are wired as adifferential amplifier, so any driftoccurring on one side of the circuitis automatically countered by a simi-lar drift on the other side, andgood stability is obtained. The cir-cuit uses the ‘bridge’ principle, withQ1-R5 forming one side of thebridge and Q2-R6 forming theother. Q1 and Q2 should ideally bea matched pair of JFETs, with IDSS

Figure 7. Source follower withoffset biasing. Zin = 44M.

Figure 8. Hybrid source follower. Zin = 500M.

Figure 9. Simple self-biasing common-source amplifier.

Figure 12. Common-source amplifier with offset gate biasing.

Figure 10. Simple headphoneamplifier.

Figure 14. Simple three-range DC voltmeter.

Figure 13. ‘Hybrid’ common-sourceamplifier.

Figure 11. General-purpose add-on pre-amplifier.

©T & L Publications, Inc. All rights reserved. Nuts & Volts Magazine/JUNE 2000 2

Figure 15.Low-drift

three-rangeDC volt-meter.

values matched within 10%. The cir-cuit is set up in the same way asthat of Figure 14.

MISCELLANEOUS JFET CIRCUITS

To conclude this month’s arti-cle, Figures 16 to 19 show a miscel-laneous collection of useful JFET cir-cuits. The Figure 16 design is thatof a very-low-frequency (VLF)astable or free-running multivibrator;its on and off periods are controlledby C1-R4 and C2-R3, and R3 and R4can have values up to 10M.

With the values shown, the cir-cuit cycles at a rate of once per 20seconds, i.e., at a frequency of0.05Hz; start button S1must be held closed forat least one second toinitiate the astableaction.

Figure 17 shows —in basic form — how aJFET and a 741 op-ampcan be used to make avoltage-controlled ampli-fier/attenuator. The op-amp is used in theinverting mode, with itsvoltage gain set by theR2/R3 ratio, and R1 andthe JFET are used as avoltage-controlled inputattenuator.

When a large nega-

tive control voltage is fed toQ1 gate, the JFET acts like a near-infinite resistance and causes zerosignal attenuation, so the circuitgives high overall gain but, whenthe gate bias is zero, the FET actslike a low resistance and causesheavy signal attenuation, so the cir-cuit gives an overall signal loss.

Intermediate values of signalattenuation and overall gain or losscan be obtained by varying the con-trol voltage value.

Figure 18 shows how this volt-age-controlled attenuator techniquecan be used to make a ‘constantvolume’ amplifier that produces anoutput signal level change of only7.5dB when the input signal level isvaried over a 40dB range (from

3mV to 300mVRMS).

The circuit canaccept input signallevels up to a maxi-mum of 500mVRMS Q1 and R4are wired in seriesto form a voltage-controlled attenua-tor that controlsthe input signallevel to commonemitter amplifier

Q2, which has its output bufferedvia emitter follower Q3.

Q3’s output is used to generate(via C5-R9-D1-D2-C4-R5) a DC con-trol voltage that is fed back to Q1’sgate, thus forming a DC negative-feedback loop that automaticallyadjusts the overall voltage gain sothat the output signal level tends toremain constant as the input signallevel is varied, as follows.

When a very small input signalis applied to the circuit, Q3’s outputsignal is also small, so negligible DCcontrol voltage is fed to Q1’s gate;Q1 thus acts as a low resistanceunder this condition, so almost thefull input signal is applied to Q2base, and the circuit gives high over-all gain.

When a large inputsignal is applied to the cir-cuit, Q3’s output signaltends to be large, so a

large DC negative control voltage isfed to Q1’s gate; Q1 thus acts as ahigh resistance under this condition,so only a small part of the input sig-nal is fed to Q2’s base, and the cir-cuit gives low overall gain.

Thus, the output level staysfairly constant over a wide range ofinput signal levels; this characteris-tic is useful in cassette recorders,intercoms, and telephone ampli-fiers, etc.

Finally, Figure 19 shows a JFETused to make a DC-to-AC converteror ‘chopper’ that produces a square-wave output with a peak amplitudeequal to that of the DC input volt-age.

In this case, Q1 acts like anelectronic switch that is wired inseries with R1 and is gated on andoff at a 1kHz rate via the Q2-Q3astable circuit, thus giving the DC-to-AC conversion. Note that Q1’s gate-drive signal amplitude can be variedvia RV1; if too large a drive is used,Q1’s gate-to-source junction startsto avalanche, causing a small spikevoltage to break through the drainand give an output even when noDC input is present.

To prevent this, connect a DCinput and then trim RV1 until theoutput is just on the verge ofdecreasing; once set up in this way,the circuit can be reliably used tochop voltages as small as a fractionof a millivolt. NV

3 JUNE 2000/Nuts & Volts Magazine ©T & L Publications, Inc. All rights reserved.

Figure 16. VLF astable multivibrator.

Figure 17. Voltage-controlled amplifier/attenuator.

Figure 18. Constant-volume amplifier.

Figure 19. DC-to-AC converter or ‘chopper’ circuit.